module SN74138 (
    input            a,
    input            b,
    input            c,
    input            en,
    output reg [7:0] y
);
  reg [2:0] adr;
  always @(a, b, c, en) begin
    adr = {c, b, a};
    if (en == 0) begin
      y <= 8'b11111111;
    end else
      case (adr)
        3'b000: y <= 8'b11111110;
        3'b001: y <= 8'b11111101;
        3'b010: y <= 8'b11111011;
        3'b011: y <= 8'b11110111;
        3'b100: y <= 8'b11101111;
        3'b101: y <= 8'b11011111;
        3'b110: y <= 8'b10111111;
        3'b111: y <= 8'b01111111;

      endcase
  end
endmodule
